Getting Started with Programmable Logic Devices (PLDs)

Okay, here’s a comprehensive article on Getting Started with Programmable Logic Devices (PLDs), aiming for approximately 5000 words:

Getting Started with Programmable Logic Devices (PLDs): A Comprehensive Guide

Programmable Logic Devices (PLDs) have revolutionized the world of digital circuit design. They offer a flexible and reconfigurable alternative to traditional fixed-function integrated circuits (ICs), allowing designers to implement complex logic functions without the need for custom-designed silicon. This guide provides a comprehensive introduction to PLDs, covering their types, architectures, design flow, programming methods, and practical applications. Whether you’re a student, hobbyist, or a seasoned engineer looking to expand your skillset, this guide will equip you with the foundational knowledge to begin working with PLDs.

1. Introduction to Programmable Logic Devices (PLDs)

1.1 What are PLDs?

A Programmable Logic Device (PLD) is an integrated circuit containing a large number of configurable logic elements (gates, flip-flops) and interconnects. Unlike fixed-function ICs, where the logic function is permanently determined during manufacturing, PLDs can be programmed (and often reprogrammed) by the user to implement a specific digital circuit. This programmability allows for rapid prototyping, design modifications, and even field upgrades, making PLDs a versatile and cost-effective solution for a wide range of applications.

1.2 Why Use PLDs?

The advantages of using PLDs over other digital circuit implementation methods (like discrete logic gates or Application-Specific Integrated Circuits – ASICs) are numerous:

Flexibility and Reconfigurability: The core strength of PLDs. You can change the logic function implemented by the device simply by reprogramming it. This is invaluable during prototyping and development, allowing for quick iterations and bug fixes.
Rapid Prototyping: PLDs drastically reduce the time it takes to go from a design concept to a working prototype. You can test and modify your design in minutes, compared to the weeks or months required for ASIC development.
Reduced Design Costs: For low to medium volume applications, PLDs are often significantly cheaper than ASICs. ASICs require substantial non-recurring engineering (NRE) costs associated with mask creation and fabrication. PLDs eliminate these costs.
Shorter Time to Market: Faster prototyping and easier design changes translate to a shorter overall time to market for products using PLDs.
Reduced Board Space: PLDs can integrate the functionality of many discrete logic chips, reducing the overall size and complexity of your circuit board.
Simplified Inventory Management: Instead of stocking numerous different fixed-function ICs, you can use a smaller number of PLD types to implement a variety of designs.
Field Upgradability: Some PLDs (especially FPGAs) can be reprogrammed in the field, allowing for bug fixes, feature additions, or even complete functional changes without hardware modifications.
IP Protection: While not as secure as an ASIC, some PLDs offer features like bitstream encryption to protect the programmed design from unauthorized copying.

1.3 Basic Building Blocks of PLDs

While the internal architectures of different PLD types vary, they all share some common building blocks:

Logic Blocks: These are the fundamental units that perform logic operations. They typically consist of:
- Look-Up Tables (LUTs): LUTs are small memory cells that implement any Boolean function of a given number of inputs. A 4-input LUT, for instance, can implement any logic function with up to four input variables. LUTs are the primary logic element in FPGAs.
- Product Terms (AND-OR Arrays): These are used in simpler PLDs like PALs and GALs. They consist of an array of AND gates followed by an array of OR gates. The AND gates generate product terms, and the OR gates combine these terms to create the desired logic function.
- Macrocells: Macrocells often combine a logic element (LUT or product term) with a flip-flop, allowing for both combinational and sequential logic implementation. They may also include additional features like output polarity selection, clock enable, and reset/preset inputs.
Interconnects: These are the programmable connections that route signals between logic blocks. The complexity and flexibility of the interconnect network significantly impact the overall capabilities of the PLD. Types of interconnects include:
- Horizontal and Vertical Routing Channels: Used in FPGAs, these channels contain wires that can be connected using programmable switches.
- Programmable Switches: These are the elements that control the connections within the interconnect network. They can be implemented using various technologies, including antifuses, SRAM cells, and EEPROM cells.
Input/Output (I/O) Blocks: These blocks provide the interface between the PLD’s internal logic and the external world. They typically include buffers, level shifters, and programmable options for input/output standards (e.g., TTL, CMOS, LVDS).

2. Types of Programmable Logic Devices (PLDs)

PLDs can be broadly categorized into several types, each with its own architecture and characteristics:

2.1 Simple Programmable Logic Devices (SPLDs)

SPLDs are the earliest and simplest type of PLDs. They typically have a relatively low logic capacity and are suitable for implementing simple combinational and sequential logic functions.

Programmable Read-Only Memory (PROM): PROMs are technically the first type of PLD. They consist of a fixed AND array (decoder) and a programmable OR array. They are programmed by “blowing” fuses to select the desired connections in the OR array. PROMs are one-time programmable (OTP) and are primarily used for implementing truth tables or lookup tables.
Programmable Logic Array (PLA): PLAs have both a programmable AND array and a programmable OR array, providing greater flexibility than PROMs. They can implement more complex logic functions. Like PROMs, early PLAs were typically one-time programmable using fuses.
Programmable Array Logic (PAL): PALs have a programmable AND array and a fixed OR array. This architecture is a compromise between the flexibility of PLAs and the simplicity of PROMs. PALs were traditionally one-time programmable, but later versions (like GALs) became reprogrammable.
Generic Array Logic (GAL): GALs are an improvement over PALs, using electrically erasable CMOS (EECMOS) technology. This allows them to be reprogrammed multiple times. GALs are still in use today for simple logic replacement and glue logic applications.

2.2 Complex Programmable Logic Devices (CPLDs)

CPLDs represent a step up in complexity from SPLDs. They offer higher logic capacity and more features, making them suitable for more complex designs.

CPLD Architecture: CPLDs typically consist of multiple SPLD-like blocks (often called function blocks or macrocell arrays) interconnected by a global routing matrix. Each function block is essentially a small PAL or PLA. The routing matrix allows signals to be routed between the function blocks.
Non-Volatility: CPLDs typically use EEPROM or Flash memory to store the configuration data, making them non-volatile. This means they retain their programming even when power is removed.
Fast Propagation Delays: CPLDs generally have relatively fast and predictable propagation delays, making them suitable for timing-critical applications.
Lower Power Consumption: Compared to FPGAs, CPLDs tend to consume less power, especially in standby mode.

2.3 Field-Programmable Gate Arrays (FPGAs)

FPGAs are the most complex and versatile type of PLD. They offer the highest logic capacity and the greatest flexibility, allowing them to implement very complex digital systems.

FPGA Architecture: FPGAs consist of a large array of configurable logic blocks (CLBs) interconnected by a programmable routing network. CLBs typically contain:
- Look-Up Tables (LUTs): LUTs are the primary logic element in FPGAs. Modern FPGAs often use LUTs with 4, 5, or even 6 inputs.
- Flip-Flops: CLBs also contain flip-flops for implementing sequential logic.
- Multiplexers: Multiplexers are used for routing signals within the CLB.
Programmable Interconnect: The FPGA’s routing network is a complex web of horizontal and vertical channels containing programmable switches. This allows for highly flexible routing of signals between CLBs.
I/O Blocks: FPGAs have sophisticated I/O blocks that support a wide range of I/O standards and can be configured for various functions (e.g., input, output, bidirectional).
Embedded Resources: Modern FPGAs often include dedicated embedded resources, such as:
- Block RAM (BRAM): On-chip memory blocks for storing data.
- Digital Signal Processing (DSP) Slices: Specialized blocks for performing high-speed arithmetic operations (e.g., multiplication, accumulation).
- Clock Management Resources: PLLs (Phase-Locked Loops) and DLLs (Delay-Locked Loops) for generating and managing clock signals.
- Embedded Processors: Some FPGAs include hard or soft processor cores (e.g., ARM, MicroBlaze) that can be integrated into the design.
Volatility: Most FPGAs use SRAM-based configuration memory, which is volatile. This means they lose their programming when power is removed and need to be reconfigured on power-up. This is typically done by loading the configuration data from an external non-volatile memory (e.g., Flash PROM). Some FPGAs use Flash or antifuse technology for non-volatile configuration.

2.4 Comparison of PLD Types

Feature	SPLDs (PAL, GAL)	CPLDs	FPGAs
Logic Capacity	Low	Medium	High to Very High
Flexibility	Low	Medium	Very High
Speed	Fast	Fast	Moderate to Fast
Power Consumption	Low	Low to Medium	Moderate to High
Non-Volatility	Some (GALs)	Yes (EEPROM/Flash)	Mostly SRAM (volatile), some Flash/Antifuse
Architecture	AND-OR Arrays	Multiple SPLD blocks	Array of CLBs
Cost	Low	Medium	Medium to High
Applications	Simple logic, glue logic	State machines, control logic	Complex systems, DSP, embedded processing

3. PLD Design Flow

The process of designing and implementing a digital circuit using PLDs involves several key steps:

3.1 Design Entry

This is the initial stage where you describe the desired functionality of your circuit. There are two primary methods for design entry:

Schematic Capture: You use a graphical editor to draw a schematic diagram of your circuit, connecting logic gates, flip-flops, and other components. This method is intuitive for simpler designs but can become cumbersome for complex circuits.
Hardware Description Languages (HDLs): HDLs are specialized programming languages used to describe the behavior or structure of digital circuits. They offer a more abstract and powerful way to represent complex designs. The two most popular HDLs are:
- VHDL (VHSIC Hardware Description Language): A powerful and widely used HDL, known for its strong typing and support for complex designs.
- Verilog: Another popular HDL, often considered easier to learn than VHDL, with a syntax similar to C.
- SystemVerilog: SystemVerilog is the superset of Verilog.

3.2 Design Synthesis

Synthesis is the process of translating the HDL code or schematic into a netlist, which is a description of the circuit in terms of the logic elements available in the target PLD. The synthesis tool performs several tasks:

Logic Optimization: The synthesis tool optimizes the logic to minimize the number of logic elements used and improve performance.
Technology Mapping: The synthesis tool maps the optimized logic to the specific logic elements (LUTs, macrocells, etc.) available in the target PLD.

3.3 Design Implementation

This stage involves transforming the netlist into a physical layout for the target PLD. It typically includes the following steps:

Placement: The placement tool determines the physical location of each logic element on the PLD chip.
Routing: The routing tool connects the logic elements together using the programmable interconnect network.
Timing Analysis: The timing analysis tool verifies that the circuit meets the required timing constraints (e.g., clock frequency, setup and hold times).

3.4 Design Verification

Verification is the process of ensuring that the design functions correctly and meets the specifications. This is typically done through simulation and testing:

Simulation: You use a simulator to apply test inputs to the design and observe the outputs. This allows you to verify the functionality of the design before programming the PLD. There are different levels of simulation:
- Functional Simulation: Verifies the logical behavior of the design without considering timing.
- Timing Simulation: Verifies the behavior of the design, including timing delays.
In-Circuit Testing: After programming the PLD, you test the actual hardware to verify that it works correctly in the target system.

3.5 Programming and Configuration

The final step is to program the PLD with the generated configuration data. This involves:

Generating a Programming File: The implementation tools generate a programming file (e.g., .bit file for FPGAs, .jed file for CPLDs) that contains the configuration data.
Programming the Device: You use a programmer (hardware device) and associated software to transfer the programming file to the PLD. The programming method depends on the PLD type:
- JTAG (Joint Test Action Group): A common serial interface used for programming and debugging many PLDs, including CPLDs and FPGAs.
- In-System Programming (ISP): Allows the PLD to be programmed while it is installed in the target system.
- Other Programming Methods: Some PLDs may use proprietary programming methods.

4. Programming Technologies

The programmability of PLDs is achieved through various underlying technologies that control the connections between logic elements and routing resources. Here are the most common:

Antifuse: An antifuse is a normally open connection that is permanently closed by applying a high voltage. This creates a low-resistance path. Antifuse-based PLDs are one-time programmable (OTP), meaning they cannot be reprogrammed. They offer high security and are resistant to radiation, making them suitable for aerospace and military applications. However, the inability to reprogram is a significant limitation.
SRAM (Static Random Access Memory): SRAM cells are used to control the state of programmable switches in many FPGAs. Each SRAM cell stores a single bit of configuration data (0 or 1). When the cell is set to 1, the corresponding switch is closed, and when it’s set to 0, the switch is open. SRAM-based PLDs are volatile, meaning they lose their configuration when power is removed. They require an external non-volatile memory (like Flash) to store the configuration data, which is loaded into the SRAM cells on power-up. The main advantage of SRAM is its reprogrammability, allowing for easy design changes and updates.
EEPROM (Electrically Erasable Programmable Read-Only Memory): EEPROM cells can be programmed and erased electrically. They are non-volatile, retaining their data even when power is off. EEPROM technology is commonly used in CPLDs. Each cell can be individually erased and reprogrammed, but the number of write/erase cycles is limited (typically 100 to 10,000 cycles).
Flash Memory: Flash memory is a type of EEPROM that offers higher density and faster write/erase speeds. It’s also non-volatile. Flash memory is used in some CPLDs and FPGAs, often as the external configuration memory for SRAM-based FPGAs. Flash memory is erased in blocks, rather than individual cells, which makes it faster for large-scale programming but less flexible for small changes. Like EEPROM, Flash memory has a limited number of write/erase cycles (typically 10,000 to 100,000 cycles).
EPROM (Erasable Programmable Read-Only Memory) EPROM’s use floating-gate transistors. They’re programmed electrically by injecting electrons onto the floating gate. Erasing requires exposure to ultraviolet (UV) light through a window on the chip, which removes the charge. EPROM is non-volatile but requires a specialized UV eraser for reprogramming, making it less convenient than EEPROM or Flash. EPROMs are largely obsolete in new designs, replaced by EEPROM and Flash.

5. Software Tools

Developing with PLDs requires specialized software tools. These tools are often provided by the PLD manufacturer (e.g., Xilinx, Intel/Altera, Lattice) and are tailored to their specific devices.

Design Entry Tools:
- Schematic Editors: Allow you to create circuit diagrams graphically.
- HDL Editors: Provide syntax highlighting, code completion, and other features to aid in writing VHDL or Verilog code.
- IP (Intellectual Property) Cores: Pre-designed and verified blocks of logic (e.g., memory controllers, processors, communication interfaces) that can be integrated into your design, saving development time.
Synthesis Tools:
- HDL Synthesizers: Translate HDL code into a netlist of logic elements. Examples include Xilinx Vivado Synthesis, Intel Quartus Prime Synthesis, and Synopsys Synplify.
Implementation Tools:
- Place and Route (PAR) Tools: Determine the physical placement of logic elements and route the connections between them on the PLD. These are usually integrated with the synthesis tools.
- Timing Analysis Tools: Analyze the timing characteristics of the implemented design to ensure it meets performance requirements.
Simulation Tools:
- HDL Simulators: Simulate the behavior of the design based on the HDL code or netlist. Examples include ModelSim (Mentor Graphics/Siemens EDA), Vivado Simulator (Xilinx), and VCS (Synopsys).
Programming Tools:
- Programmers/Debuggers: Hardware devices and associated software used to program the PLD and debug the design. This often includes JTAG interfaces. Examples are Xilinx Platform Cable USB, Intel/Altera USB-Blaster.
Integrated Development Environments (IDEs): Modern PLD development often relies on comprehensive IDEs that integrate all the above tools into a single environment. Examples include:
- Xilinx Vivado Design Suite: For Xilinx FPGAs and SoCs.
- Intel Quartus Prime: For Intel (formerly Altera) FPGAs and CPLDs.
- Lattice Diamond: For Lattice FPGAs and CPLDs.
- Microsemi (Microchip) Libero SoC Design Suite For Microsemi (Microchip) FPGAs.

6. Getting Started: Practical Steps

Now that we have a solid theoretical understanding, let’s outline the practical steps to start working with PLDs:

6.1 Choose a PLD Type and Vendor

Consider Your Project Requirements:
- Logic Complexity: How complex is your design? A simple state machine might only need a CPLD, while a complex digital signal processing application will require an FPGA.
- Speed Requirements: How fast does your circuit need to operate? CPLDs generally offer faster and more predictable timing than FPGAs, but high-performance FPGAs can achieve very high speeds.
- Power Consumption: Is power consumption a critical factor? CPLDs typically consume less power than FPGAs.
- I/O Requirements: How many I/O pins do you need, and what I/O standards do you need to support?
- Non-Volatility: Do you need the design to retain its configuration when power is removed?
- Cost: What is your budget? SPLDs and CPLDs are generally cheaper than FPGAs.
Select a Vendor: The major PLD vendors are Xilinx, Intel (formerly Altera), Lattice Semiconductor, and Microchip (formerly Microsemi). Each vendor offers a range of PLD families with different features and price points. The choice of vendor often depends on factors like tool availability, support, and personal preference.
Choose a Specific Device: Once you’ve chosen a vendor and PLD type, select a specific device that meets your requirements. Consider factors like logic capacity, number of I/O pins, available embedded resources, and package type.

6.2 Obtain the Necessary Hardware

Development Board: A development board is a pre-designed circuit board that contains the PLD, along with supporting components like clock sources, memory, I/O connectors, and programming interfaces. Development boards are an excellent way to get started with PLDs, as they provide a readily available platform for experimentation and prototyping. Choose a board that is compatible with your selected PLD.
Programmer: You’ll need a programmer to transfer the configuration data to the PLD. Many development boards include an on-board programmer (often a USB-JTAG interface). If not, you’ll need to purchase a separate programmer.
Cables and Connectors: Make sure you have the necessary cables and connectors to connect the development board to your computer and any external peripherals.

6.3 Install the Software Tools

Download and Install the IDE: Download the appropriate IDE from the PLD vendor’s website. This typically includes all the necessary tools for design entry, synthesis, implementation, simulation, and programming.
Obtain Licenses: Some PLD software tools require licenses. Free or evaluation licenses are often available for students and hobbyists. For professional use, you may need to purchase a commercial license.
Install Drivers: Install any necessary drivers for the programmer and development board.

6.4 Learn a Hardware Description Language (HDL)

Choose an HDL: Decide whether to learn VHDL or Verilog. Both are powerful HDLs, and the choice often comes down to personal preference or the requirements of your project or organization. Verilog is generally considered easier to learn initially, while VHDL is often favored for very large and complex projects due to its stricter syntax.
Find Learning Resources: There are numerous online tutorials, books, and courses available for learning VHDL and Verilog.
Practice: The best way to learn an HDL is to practice writing code. Start with simple examples and gradually work your way up to more complex designs.

6.5 Start with Simple Projects

Blinking an LED: This is the classic “Hello, World!” project for PLDs. It teaches you the basics of design entry, synthesis, implementation, and programming.
Basic Logic Gates: Implement simple logic gates (AND, OR, XOR, etc.) to understand how to use LUTs or product terms.
Simple State Machine: Design a simple state machine (e.g., a counter or a traffic light controller) to learn how to implement sequential logic.

6.6 Explore Advanced Features

Embedded Resources: Learn how to use the embedded resources available in your PLD (e.g., BRAM, DSP slices, clock management resources).
IP Cores: Explore the available IP cores and learn how to integrate them into your designs.
Advanced Design Techniques: Learn about advanced design techniques, such as pipelining, clock domain crossing, and constraint-driven design.
Soft Processors: If your FPGA has soft processor capabilities, learn how to integrate a processor into your design and write software for it.

6.7 Troubleshooting

Compilation Errors: Learn to understand and fix compilation errors in your HDL code.
Simulation: Use simulation to debug your design and identify functional errors.
Timing Analysis: Use timing analysis to identify and fix timing violations.
On-Chip Debugging: Use on-chip debugging tools (e.g., Signal Tap in Quartus, ChipScope in Vivado) to monitor signals inside the PLD during runtime.

7. Example Project: A Simple Counter

Let’s illustrate the process with a simple Verilog example of a 4-bit counter:

“`verilog
module counter(
input clk,
input reset,
output reg [3:0] count
);

always @(posedge clk or posedge reset) begin
if (reset) begin
count <= 4’b0000; // Reset to 0
end else begin
count <= count + 1; // Increment count on clock edge
end
end

endmodule
“`

Explanation:

module counter(...): Defines a module named counter with inputs clk (clock), reset, and a 4-bit output count.
input clk, input reset: Declares clk and reset as input signals.
output reg [3:0] count: Declares count as a 4-bit registered output. reg indicates that the value is stored in a flip-flop.
always @(posedge clk or posedge reset): This is a sensitivity list. The always block executes whenever there is a positive edge on either clk or reset.
if (reset) begin ... end else begin ... end: This is a conditional statement. If reset is high, the counter is reset to 0. Otherwise, the counter is incremented on each positive clock edge.
count <= 4'b0000: Assigns the binary value 0000 to the count register.
count <= count + 1: Increments the count register.

Steps to implement this on a PLD (using Xilinx Vivado as an example):

Create a New Project: Start Vivado and create a new project, selecting your target FPGA device.
Add Source: Create a new Verilog source file (e.g., counter.v) and paste the code above.
Synthesis: Run synthesis to translate the Verilog code into a netlist.
Implementation: Run implementation (place and route) to map the design to the FPGA resources.
Generate Bitstream: Generate the bitstream file (programming file).
Program Device: Connect your development board and use the Hardware Manager in Vivado to program the FPGA with the generated bitstream.
Connect to Output: Connect LEDs to the output pins corresponding to count[3:0] on your development board.

After programming, you should see the LEDs counting up in binary from 0 to 15 on each clock cycle. You can modify the code to change the counter’s behavior (e.g., count down, change the modulus). This simple example demonstrates the basic workflow for PLD development.

8. Conclusion

Programmable Logic Devices (PLDs) provide a powerful and flexible platform for digital circuit design. From simple SPLDs to complex FPGAs, they offer a range of options to suit various applications. By understanding the different types of PLDs, their architectures, design flow, and programming methods, you can leverage their capabilities to create innovative and efficient digital systems. This guide has provided a comprehensive foundation for getting started with PLDs. Remember to start with simple projects, gradually increase complexity, and continuously learn and explore the vast capabilities of these versatile devices. The world of digital design with programmable logic is open for you to explore and create!

Leave a Comment Cancel Reply